`timescale 1ns/100ps

module clock_mod;

parameter SYSCLK_PERIOD = 10;

reg SYSCLK;
reg nRESET;

initial
begin
	SYSCLK = 0;
	nRESET = 0;
end


/*iverilog */
initial
begin            
    $dumpfile("clock.vcd");        //生成的vcd文件名称
    $dumpvars(0, clock_mod);    //tb模块名称
end
/*iverilog */

initial

begin
	#(SYSCLK_PERIOD * 10 )
        nRESET = 1'b1;
	#1000
		$finish;
end

always @(SYSCLK)
begin
	#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end

endmodule
